PIC16F916-I/ML【PDF 14/229 页】IC PIC MCU FLASH 8KX14 28QFN

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Sheet目录3862

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196

8018P–AVR–08/10

ATmega169P

Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

Bit 4 – RXENn: Receiver Enable n

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn, and UPEn Flags.

Bit 3 – TXENn: Transmitter Enable n

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, that is,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxD port.

Bit 2 – UCSZn2: Character Size n

The UCSZn2 bits combined with the UCSZ1n:0 bit in UCSRnC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

Bit 1 – RXB8n: Receive Data Bit 8 n

RXB8n is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

Bit 0 – TXB8n: Transmit Data Bit 8 n

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

19.11.4

UCSRnC – USART Control and Status Register n C

Bit 6 – UMSELn: USART Mode Select n

This bit selects between asynchronous and synchronous mode of operation.

Bit 5:4 – UPMn[1:0]: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Bit

765

432

(0xC2)

–

UMSELn

UPMn1

UPMn0

USBSn

UCSZn1

UCSZn0

UCPOLn

UCSRnC

Read/Write

R/W

Initial Value

Table 19-8.

UMSELn Bit Settings

UMSELn

Mode

Asynchronous Operation

Synchronous Operation

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